This invention relates generally to shared memory systems for use in multiprocessing systems, and more particularly to a system and method for initializing and testing all interfaces and memory in a data processing system having multiple memory banks or a memory module partitioned into logical memory units.
Large-scale data processing systems typically utilize a tremendous amount of memory. This is particularly true in multiprocessing systems where multiple processing units are implemented. There are several memory methodologies known in the art that provide for efficient use of memory in such multiprocessing environments. One such memory methodology is a distributed memory where each processor has access to its own dedicated memory, and access to another processor""s memory involves sending messages via an inter-processor network. While distributed memory structures avoid problems of contention for memory and can be implemented relatively inexpensively, it is usually slower than other memory methodologies, such as shared memory systems.
Shared memory is used in a parallel system, or multiprocessing, system, and can be accessed by more than one processor. The shared memory is connected to the multiple processing unitsxe2x80x94typically accomplished using a shared bus or network. Large-scale shared memories may be designed to cooperate with local cache memories associated with each processor in the system. Cache consistency, or coherency, protocols ensure that one processor""s cached copy of a shared memory location is invalidated when another processor writes to that location.
In order to effectively and efficiently utilize shared memory systems, it may be desirable to configure the shared memory in a predetermined manner prior to use. For example, many shared memory systems employ memory partitioning for executing certain tasks. Generally, a memory partition is a contiguous area of memory within which tasks are loaded and executed, and memory partitioning is the act of designating such memory partitions. A partition includes predetermined characteristics such as a name, a defined size, and a starting address. Where shared memory systems associated with multiprocessing systems are very large, a great deal of overhead may be associated with such memory partitioning. It would therefore be desirable to provide for partitioning the shared memory in the most efficient and timely manner possible.
The data storage in such memory systems should also be capable of initialization to a predetermined state when desired, such as upon initial power application. Other memory locations may also require initialization, such as a directory storage area. Directory storage is used in directory-based cache coherency systems to store cache line state information. A cache line is a predetermined-size data packet that is transferred between the cache memory and the main, shared memory. Extremely large memories can include a correspondingly large volume of cache line storage, which must be tracked by the directory storage. Again, a great deal of time may be consumed during the initialization stage in a computing environment, and it would be desirable to provide a manner of efficiently initializing the shared memory system.
In order to ensure proper operation of the multiprocessing system, testing of the memory to locate and identify faulty memory locations is critical. A faulty storage location can have devastating effects on the operation of the system, particularly where data, executable programs, cache directory structures and the like, are all ultimately reliant on properly functioning memory. However, as is true for initialization functions, pre-processing functions such as memory testing for large-scale memory systems creates additional overhead, causing undesirable start-up delays.
The aggregate effect of performing various types of partitioning, initializing and testing in computer systems having tremendous storage capability is an undesirably lengthy initialization phase. Further, prior art systems typically perform a fixed initialization or testing function without affording flexibility to perform more specific or ad hoc test functions that were not thought of at the time at which fixed test functions were originally established.
It would therefore be desirable to provide an efficient system and method for initializing and testing extensive memory systems, in order to reduce pre-processing operation delays. The present invention provides a high performance mechanism and method for cooperatively testing and initializing a shared memory system having multiple memory banks, and provides flexibility to later afford an opportunity to include newly-created test functions. The present invention therefore provides a solution to shortcomings of the prior art, and offers numerous other advantages over the prior art.
The present invention provides a system and method for testing and initializing a memory including multiple memory banks or a memory module partitioned into logical memory units. Testing in accordance with the present invention provides for parallel test activities for testing data storage, directory storage, and address and data interfaces.
In accordance with another embodiment of the invention, a memory test and initialization circuit for testing and initializing the memory and memory interfaces in a data processing system is provided. The memory is physically divided into separate memory banks, or alternatively is divided into a plurality of logical memory units. The circuit includes a plurality of exerciser testers, one for each of the plurality of memory banks. Each of the exerciser testers includes an address generator to generate a sequence of memory bank addresses to successively address each of the memory banks in a cyclic manner. Therefore, each address generator addresses a first memory bank, followed by a second memory bank and so forth until each memory bank has been addressed, at which time the address generator again addresses the first memory bank. Each of the address generators in the test and initialization circuit performs this type of cyclic memory bank addressing, however each of the address generators concurrently addresses a different one of the memory banks. A data pattern generator is coupled to a corresponding one of the address generators to receive a data pattern control signal upon each output of each of the memory bank addresses generated by its corresponding address generator. The data pattern generator outputs a unique data pattern to the memory bank identified by the memory bank address in response to each occurrence of the data pattern control signal. In one embodiment, the data pattern generated is an incrementing data pattern, where the increment occurs each time the memory bank address changes. The circuit also includes a plurality of address initialization registers, one for each of the plurality of exerciser testers. Each of the address initialization registers stores an initial memory bank address for one of the memory banks. In this manner, each of the address generators is preset to initially address a different one of the memory banks, and each address generator addresses each memory bank in a cyclical fashion. Therefore, each memory bank is addressed by a different one of the address generators at any given time, which provides for concurrent testing of all memory banks and memory interfaces.
In accordance with another embodiment of the invention, a method for performing test and initialization of a memory having a plurality of memory banks is provided. The method includes concurrently generating a plurality of memory bank addresses from a plurality of address generators, wherein each of the concurrently generated memory bank addresses targets a different one of the plurality of memory banks. The memory bank addresses are provided from each of the address generators to each of the plurality of memory banks in a cyclical fashion. An incrementing data pattern is generated for each of the memory bank addresses targeting a particular one of the memory banks, wherein each of the data patterns is written to the memory bank addressed by its corresponding memory bank address. The data patterns are subsequently read back from the plurality of memory banks in the same sequence in which the data patterns were written to the plurality of memory banks. The data patterns read back from the memory banks are then compared to expected data patterns to verify memory and memory interface performance. In more specific embodiments of the invention, the initialization process includes additional initialization steps for initializing SDRAM memory, including initializing hardware registers to a predetermined logic state, precharging each of the SDRAM memory banks, performing a memory refresh operation on each of the SDRAM memory banks, and programming each of the SDRAM memory banks to conform to a desired mode of operation.
Still other objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. As will be realized, the invention is capable of other and different embodiments, and its details are capable of modification without departing from the scope and spirit of the invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.